The present invention relates to a disk array device and its data processing method and more particularly to a technique that is effectively applicable for a data processing method capable of realizing a double writing system of data while a processing of writing into a cache memory (through a switch) is reduced.
As a result of consideration by the inventors of this invention, the following techniques have been considered as conventional disk array device and its data processing.
For example, as regards the data processing technique of the conventional disk array device, there is such a technique that the cache memory for storing temporarily data between an upper device and a memory unit of the disk array device is constructed into a duplex system in order to correspond to improvement of the performance of users, so that data transferred from the upper device is stored into each cache memory so as to keep data in the duplex system for storage. According to such a technique, a switch connecting method is adopted for an internal data transfer path, which connects between the interface of the upper device and the duplex system cache memory. Under this switch connecting method, a connection between the interface of the upper device and the duplex system cache memory, and a connection between the interface of a memory unit and the duplex system cache memory are respectively made one-on-one through a switch portion (see Japanese Patent Laid-open No. 11-312126).
As a result of consideration by the above-mentioned inventors, as regards the conventional disk array device and its data processing technique, the following matters have been made evident.
For example, according to the data processing technique of the conventional disk array device, since the connection between the interface of the upper device and the duplex system cache memory, and the connection between the interface of the memory unit and the duplex system cache memory are made one-on-one through the same switch portion, there is the problem that double writing of the same data consumes double power as compared to the case where a switch region is single-written.
That is, when storing data transferred from the upper device into the duplex system cache memory, the switch portion needs a region for storing data sent from the upper device, into one of the cache memories from the interface of the upper device through the switch portion, and another region for storing the same data into the other cache memory through the same switch. Consequently, the region for the switch portion needs to be in double amount when the same data is executed in a double writing system as compared to the case where the same data is executed in a single writing system. For the reason, it is desirable to equalize the band region of the switch portion to the single writing system along with a concept of the double writing system.